In electronic circuits, there are very many signals passing round, being moved from one component or element to another, as well as moving within components. In some cases, different parts of the circuit represent different clock domains, being clocked at different clock speeds or timings. In general, control signals and status signals pass from one clock domain to another and/or are passed to some centralised clocking and power state controller module. In general, these status and control signals have to be synchronised. A particular example of this is system state control.
There are in addition very many circuits and devices that use interrupts during operation. In simple terms and as a typical example, an interrupt is an asynchronous signal sent to a processor, such as a central processing unit or CPU, indicating the need for attention. In general, a hardware interrupt causes the processor (typically at the next clock cycle) to save its state of execution and begin execution of an interrupt handler to service the interrupt request. Typically, since no external devices or other parts of the circuit share the same clock as the processor or CPU, all external interrupts, i.e. interrupts that are external to the processor, are said to be asynchronous.
In general, asynchronous interrupts are synchronised to the destination domain (such as a processor) using synchronisers to avoid metastability problems and glitches or erroneous events. A “glitch” is an undesired transition in a signal that occurs before the signal settles to its intended value. For processors, the interrupts are asynchronous events that can interrupt the processor execution or wake it up, for example. Within a processor, there are only a few interrupt lines. However, in larger systems, where there may be several or many components sending interrupts to the processor, an interrupt controller (IC) can be used, typically to handle hundreds of interrupts potentially being passed to the processor. An example of the organisation is shown schematically in FIG. 1. The incoming interrupts 1 are first synchronised in an interrupt synchroniser 2 as required, then fed 3 to the interrupt controller 4, which in turn sends 5 the controlled interrupts to the actual processor or CPU 6.
However, a problem is that the hundreds of interrupts typically come from different clock domains to the interrupt controller. To avoid the metastability issue, all the interrupts are synchronised using free-running clocks. However, in practice, from the hardware perspective, the interrupt values may not change very often. To save power, the processor can be put into an idle mode when not required to be active, and then woken upon some interrupt being asserted. However, the synchroniser clocks for the interrupts cannot be put into an idle mode or their outputs disabled at a time associated with the idle mode of the processor because they are asynchronous events relative to the processor, and also relative to the interrupt controller. Accordingly, conventionally, the interrupt synchronisers and synchroniser clocks continue to run, which consumes significant amounts of power. This is a particular problem for battery-operated devices, including for example mobile wireless devices such as mobile or cell phones (including so-called “smart phones”), personal digital assistants, pagers, tablet and laptop computers, etc., etc.
In U.S. Pat. No. 4,615,005, there is disclosed a data processing apparatus with clock signal control for reduced power consumption. A clock supplying circuit which supplies actuating clock signals to a main CMOS processor of the apparatus is locked and unlocked according to received interrupts, thereby controlling the power consumption of the CMOS processor.